the hi-8020 & hi-8120 high voltage display drivers are functional replacements for the ami s5420 and micrel mic8013/8014 series. these cmos prod- ucts are designed to drive liquid crystal displays by converting 5 volt serial data to parallel segment and backplane waveforms with amplitudes up to 30 volts. the hi-8020 & hi-8120 differ from the hi-8010 by only the shift register clock and chip select gating logic. the hi-8020 has ttl logic inputs whereas the hi-8120 has cmos logic inputs. both devices can drive up to 38 segments and have 3 possible shift register data taps to provide options to cascade devices for larger displays. data is clocked into a 38 stage shift register and parallel latched before the output translators by a load input. the hi-8020 & hi-8120 are available in ceramic leadless chip carriers and plastic plcc packages. dichroic liquid crystal displays standard liquid crystal displays vacuum fluorescent displays mems drivers applications 5 volt input translated to 30 volts or less pin-out adaptable to drive 30, 32 or 38 lcd segments rc oscillator or high voltage (bp) clock input ttl compatible inputs (hi-8020 only) low power consumption industrial (-40c to +85c) & military (-55c to +125c) temperature ranges pin for pin compatible with the micrel mic8010/8011 series and the ami s4520 series drivers cascadable military level processing available cmos compatible inputs (hi-8120 only) pin configuration (top view) functional block diagram general description (see page 4 for additional package pin configurations) features bp oscillator divider voltage translator high voltage buffer 38 stage shift register 38 bit latch voltage translators high voltage drivers segments data in clk le dout 38 dout 32 dout 30 din cl cs ld lcd? lcd? opt november 2007 39 38 37 36 35 34 33 32 31 30 29 s17 s16 s15 s14 s13 s12 s11 s9 s8 v s10 ee s27 s28 s29 s30 s31 s32 n/c v ld ss cs cl 7 8 9 10 11 12 13 14 15 16 17 s26 s25 s24 s23 s22 s21 s20 dout 32 bp s19 s18 din lcd? lcd?opt v s1 s2 s3 s4 s5 s6 s7 dd 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 hi-8020j-85 & hi-8120j-85 44 - pin plastic plcc (ds8020 rev. g) 11/07 hi-8020, hi-8120 cmos high voltage display driver holt integrated circuits www.holtic.com
functional description whenever a logic "0" is applied to the chip select ( ) input, one bit of data is clocked into the shift register from the serial data input (din) with each negative transition of the clock ( ) input. a logic "1" present at the load (ld) input will cause a parallel transfer of data from the shift register to the data latch. if the load (ld) input is held high while data is clocked into the shift register, the latch will be transparent. all four logic inputs are ttl compatible on the hi-8020 and cmos compatible on the hi-8120. to display segments, a logic "1" is stored in the appropriate shift register bit position, and the segment output is out-of- phase with the backplane. the backplane output functions in 1 of 2 modes; externally driven or self-oscillating. when the lcd? input is externally driven with the lcd?opt input open circuit (figure 2), the backplane output will be in-phase with lcd?. utilizing the self-oscillating mode, inputs lcd? and lcd?opt are tied together and connected to an rc circuit (figure 3). a 150k resistor with a 470pf capacitor generates an approximate backplane frequency of 100hz. the lcd?/lcd?opt oscillator frequency is divided by 256 to determine the backplane output frequency. the resistor value (r) must be at least 30k for proper self-oscillator operation. for displays having a number of segments greater than 38, two or more of the display drivers may be cascaded together by connecting the serial data output (dout) from the first driver, to the serial data input (din) of the following driver, etc.(see figures 2 & 3). data out (dout) will change state cs cl hi-8020/hi-8120 series internal oscillator circuit to backplane translator and driver 256 c r lcd? opt lcd? figure 1. q on the rising edge of the clock ( ). clock ( ), load (ld) and chip select ( ) should be tied in common with each other, respectively, between all cascaded display drivers. cl cl cs timing diagram t csh t css t ds t dh t cl t cdo t ls t lw t csl t lcs cl input din input cs input ld input dout output valid valid valid valid valid holt integrated circuits 2
hi-8020/hi-8120 series absolute maximum ratings voltages referenced to vss = 0v dc electrical characteristics ac electrical characteristics vdd = 5v, vee = -25v, vss = 0v, ta = operating temperature range (unless otherwise specified). parameter symbol vdd min typ max units cl clock period t 5v 1200 ns clock pulse width t 5v 520 ns data in - setup t 5v 50 ns data in - hold t 5v 400 ns chip select - setup to clock t 5v 200 ns chip select - hold to clock t 5v 450 ns load - setup to clock t 5v 500 ns chip select - setup to load t 5v 300 ns load pulse width t 5v 500 ns chip select - hold to load t 5v 300 ns cw ds dh css csh ls csl lw lcs data out valid, from clock t 5v 800 ns cdo note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. vdd........................ vee................ supply voltage vdd-35v to 0v 0v to 7v voltage at any input, except lcd?..-0.3 to vdd+0.3v voltage at lcd? input...............vdd-35 to vdd+0.3v dc current any input pin...................................10 ma power dissipation......................................................300 mw operating temperature range - hi-temp/mil..-55 to +125c storage temperature range...........................-65 to +150c operating temperature range - industrial........-40 to +85c vdd = 5v, vee = -25v, vss = 0v, ta = operating temperature range (unless otherwise specified). parameter symbol condition min typ max units operating voltage vdd 3.0 7.0 v supply current (static, no load) idd @+85c, 225 a @ +125c, 300 iee @ +125c, f =100hz 150 a input low voltage, hi-8020 (except lcd?) vil 0 0.8 v input high voltage, hi-8020 (except lcd?) vih 2 vdd v input low voltage, hi-8120 (except lcd ) vil 0 0.3 vdd v input high voltage, hi-8120 (except lcd input low voltage (lcd?) vilx vee 3 v input high voltage (lcd?) vihx 3.5 vdd v input current iin vi n=0to5v 1 a input capacitance (not tested) ci 5 pf segment output impedance rseg il = 10a 10 15 k backplane output impedance rbp il = 10a 450 600 data out current: idoh source current, voh = 4.5v -0.6 ma idol sink current, vol = 0.5v 0.6 ma f =0hz f =0hz a ? ?) vih 0.7 vdd vdd v bp bp bp ttl ttl cmos cmos holt integrated circuits 3
symbol function description vss power 0 volts input logic input chip select input logic input clocks shift register on negative edge and dout pins on positive edge ld input logic input segment outputs equal shift register data if load is high din input logic input shift register data input lcd0 input analog input display clock input and is always bonded out. can swing from vee to vdd lcd0opt output analog output bonded out only if an rc oscillator is required vdd power 5 volts vee power 0 volts to -30 volts dout output logic output selected pinout can provide shift register taps at positions 30, 32, 34, or 38 bp output display drive output low resistance drive for the backplane and swings from vdd to vee segments output display drive output high resistance drive for each segment and swings from vdd to vee cs cl cascading - ext. oscillator hi-8020/hi-8120 series cascading - rc oscillator din hi-8020j-85 cs lcd? cl ld dout bp segments 1-33 din hi-8020j-85 cs lcd? cl ld dout bp segments 33-64 din hi-8020j-85 cs lcd? cl ld dout bp segments 65-96 back plane ld cl cs din hi-8120j-85 cs lcd? cl ld dout bp segments 1-32 lcd? opt din hi-8120j-85 cs lcd? cl ld dout bp segments 33-64 lcd? opt din hi-8120j-85 cs lcd? cl ld dout bp segments 65-96 lcd? opt back plane 470pf 150k ld cl cs figure 2 figure 3 additional hi-8020/hi-8120 pin configurations (see page 1 for the 44-pin plastic plcc) 6 5 4 3 2 1 48 47 46 45 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 hi-8020cli-61 hi-8120cli-61 HI-8020CLM-62 & hi-8120clm-62 48 - pin ceramic lcc 6 5 4 3 2 1 48 47 46 45 44 43 19 20 21 22 23 24 25 26 27 28 29 30 cl ld din s37 s38 s1 s2 s3 s4 s5 v dd s26 s25 s24 s19 s18 s17 s23 s22 s21 s20 dout 38 bp s16 s15 v s14 s13 s12 s11 s10 s9 s8 s7 s6 ee 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 s27 s28 s29 s30 s31 s32 s33 s34 s35 s36 v ss cs hi-8020cli-63 hi-8120cli-63 hi-8020clm-64 & hi-8120clm-64 48 - pin ceramic lcc pin descriptions 42 41 40 39 38 37 36 35 34 33 32 31 s16 s15 v s14 s13 s12 s11 s10 s9 s8 s7 s6 ee s27 s28 s29 s30 s31 s32 s33 s34 s35 s36 v ss cs lcd? / lcd?opt cl ld din lcd? s37 s38 s1 s2 s3 s4 s5 v dd s26 s25 s24 s19 s18 s17 s23 s22 s21 s20 dout 38 bp holt integrated circuits 4
hi-8020/hi-8120 series ordering information hi - 8 j - 85 (44-pin plastic j-lead plcc) (44j) xxx x hi - 8 (48-pin ceramic leadless chip carrier) (48s) xxx xxx-xx part number lead finish 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank part number master/ slave temperature range flow burn in lead finish tin / lead (sn / pb) solder gold (pb-free, rohs compliant) tin / lead (sn / pb) solder clm - 62 master cli - 63 slave clm - 64 slave -55c to +125c -40c to +85c -55c to +125c m i m yes no yes gold (pb-free, rohs compliant) cli - 61 master -40c to +85c i no temperature range flow burn in -40c to +85c no i -40c to +85c no i part number input logic number of segments master/ slave 8120 cmos 32 both 8020 ttl 32 both part number input logic number of segments 8120 cmos 38 8020 ttl 38 holt integrated circuits 5
hi-8020/hi-8120 series semi-custom packaging the above part numbers represent the standard configurations of the hi-8020 & hi-8120 products. they can also be provided with a varied number of output segments (30, 32 and 38), with either industrial or military screening and in a wide variety of packages. listed below are currently available packages. please contact the holt sales department for your specific requirements. package # description leads plastic dual-in-line (pdip) 40 48 plastic quad flat pack (pqfp) 52 plastic j-lead chip carrier (plcc) 44 ceramic dual-in-line (cdip) 40 48 ceramic leadless chip carrier (lcc) 40 48 ceramic j-lead chip carrier 44 48 ceramic leaded chip carrier 40 48 holt integrated circuits 6
hi-8020/hi-8120 package dimensions 48-pin ceramic leadless chip carrier inches (millimeters) package type: 48s bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) pin 1 ident. pin 1 ident. .090 (2.286) .563 .009 (14.300 .228) sq. .040 .007 (1.016 .178) max .040 (1.016) bsc .020 (.508) typ .020 (.508) typ 44-pin plastic plcc inches (millimeters) package type: 44j bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) pin no. 1 ident .045 x 45 .045 x 45 pin no. 1 .173 .008 (4.394 .203) .690 .005 (17.526 .127) sq. .610 .020 (15.494 .508) .031 .005 (.787 .127) .653 .004 (16.586 .102) sq. .017 .004 (.432 .102) .050 (1.27) bsc detail a r .010 .001 (.254 .03) .020 (.508) min see detail a .035 .010 (.889 .254) holt integrated circuits 7
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